Design of High Speed Area Optimized Binary Coded Decimal Digit Adder and Multiplier

Decimal arithmetic is very important for computations in financial and commercial transactions which include banking system, tax calculation, billing etc. Decimal arithmetic algorithm mainly includes decimal addition and multiplication. The main problem in the existing decimal arithmetic is the need for correcting the result as it is in the binary form. This causes the implementation area to be large and increases the delay. In this paper, a high speed area optimized binary coded decimal digit adder and multiplier are designed. The proposed adder and multiplier have improved delay and area due to the employed correction free mechanism and the result thus obtained is in BCD form without adding any correction values. This paper also presents the multilevel optimization of the Boolean expressions. It minimizes the layout area, delay and increases the performance.